Equalization pulse generating circuit for memory device

ABSTRACT

A circuit for generating equalization pulses for a memory device is disclosed, which prevents formation of a short circuit between a Vdd potential and a Vss potential when two address transition signals are successively generated, and which generates the equalization pulses by using address transition pulses and by reducing the access time of the memory device. The equalization pulse generating circuit includes a NAND circuit section for outputting a NAND logic of address transition signals under address transitions to an equalization pulse generating node, a delay circuit section for delaying an output of the equalization pulse generating node for a certain period of time, so as to generate at least one delayed output signal, and a maintaining circuit section for logically processing the delayed output signal of the delay circuit section and the NAND logic output of the NAND circuit section, so as to maintain the state of the equalization pulse generating node in the same state for a certain period of time.

FIELD OF THE INVENTION

The present invention relates to an I/O (input/output) line equalizationpulse generating circuit. Particularly, the present invention relates toa circuit for generating pulses such that an optimum equalization timeis ensured.

DESCRIPTION OF THE BACKGROUND ART

Recently, memory devices accommodate higher and higher frequencysignals, and in this context, it is required that the input and outputbe driven without noise or delay even if the address transition becomesfaster. An I/O line equalization circuit is used almost in every memorydevice for optimizing the equalization time when an address transitionsignal is generated to output an equalization pulse.

However, the equalization pulse generator which is used in theconventional memory device is unsuitable in the equalization time forthe case where the address transition is fast. Therefore, it became anunstabilizing problem in driving the I/O line.

An address transition pulse generating circuit is used in theconventional memory devices as disclosed in U.S. Pat. No. 4,614,883.

As shown in FIG. 1, the equalization pulse generating circuit isconstituted as follows. That is, a Plurality of MOS transistors areconnected to address transition signals. Thus, if the address transitionsignal is shifted, then an EQ signal is formed, so that the I/O lineswould be equalized.

FIG. 2 is a timing chart for the equalization pulse generating circuitfor the conventional memory devices.

The conventional technique will be described referring to FIGS. 1 and 2.

As shown in FIG. 1, this conventional circuit includes a first NORcircuit section A consisting of five transistors Q(A), Q(B), Q(C), Q(D)and Q(E);

a second NOR circuit section B consisting of inverters INV(A), INV(B),INV(C) and INV(D), NAND gates ND(A) and ND(B), and a NOR gate NOR(A);

a latching section C consisting of two inverters INV(E) and INV(F);

a charging section D consisting of a NAND gate ND(C), an inverter INV(G)and two transistors Q(F) and Q(G);

a delay circuit section E consisting of an inverter INV(H), a delaycircuit T and a NOR gate NOR(B); and

an inverter INV(I).

In the first NOR gate circuit section A, the gate of the transistor Q(A)is connected to an inverted chip selecting signal CSD, and the gate ofthe transistor Q(B) receives an address transition signal ATXO. Further,the gate of the transistor Q(C) receives an address transition signalATX1, and the gate of the transistor Q(D) receives an address transitionsignal ATX2, while the gate of the transistor Q(E) receives an addresstransition signal ATX3. The sources of the transistors Q(A), Q(B), Q(C),Q(D) and Q(E) are all connected to Vss, while the drains of thesetransistors are connected to a node N1.

In the latching section C, the input terminal of the inverter INV(E) isconnected to the node N1, and the output terminal of the inverter INV(E)is connected to the input terminal of the inverter INV(F), while theoutput terminal of the inverter INV(F) is connected to the node N1 inturn.

In the second NOR circuit section B, the input terminal of the inverterINV(D) is connected to an address transition signal ATXO, while theinput terminal of the inverter INV(C) is connected to an addresstransition signal ATX1. Further, the output terminal of the inverterINV(D) and the output terminal of the inverter INV(C) are connectedrespectively to the two input terminals of the NAND gate ND(A). Theinput terminal of the inverter INV(B) is connected to an addresstransition signal ATX2, while the input terminal of the inverter INV(A)is connected to an address transition signal ATX3. Further, the outputterminals of the inverters INV(A) and INV(B) are connected respectivelyto two input terminals of the NAND gate ND(B). Further, the outputterminals of the NAND gates ND(A) and ND(B) are connected respectivelyto two input terminals of the NOR gate NOR (A), while an output signalINH of the NOR gate NOR(A) is connected to the charging section D.

The input terminal of the inverter INV(I) is connected to the node N1,while the output terminal of the inverter INV(I) generates equalizationpulses EQ.

In the delay circuit section E, the input terminal of the inverterINV(H) is connected to the output terminal of the inverter INV(I), andthe output terminal of the inverter INV(H) is connected to the inputterminal of the delay device T. The chip selecting signal CSD and theoutput terminal of the delay device T are connected to two inputterminals of the NOR gate NOR(B), while the output signal SRE of the NORgate NOR(B) is connected to the charging section D.

In the charging section D, the output terminal of the NOR gate NOR(A) ofthe second NOR circuit section B and the output terminal of the NOR gateNOR (B) of the delay circuit section E are connected respectively to twoinput terminals of the NAND gate ND (C) . The output signal RE of theNAND gate ND(C) is connected to the input terminal of the inverterINV(G) and to the gate of the transistor Q(F). The source of thetransistor Q(F) is connected to Vdd, and its drain is connected to thenode N1. The output terminal of the inverter INV(G) is connected to thegate of the transistor Q (G), and the drain of the transistor Q(G) isconnected to Vdd, while its source is connected to the node N1.

The conventional circuit constituted as described above operates in thefollowing manner.

When the chip selecting signal is enabled in a state where the addresstransition did not occur, the initial values are as follows.

As shown on the left side of FIG. 2, when a chip selecting signal isgenerated as the signal CSD being shifted from high to low, the outputof the NOR gate NOR(B) becomes high, and therefore, the signal SREbecomes high. Since the four address transition signals are all low, theoutputs of the NAND gates ND(A) and ND(B) become low. Consequently, theinputs of the NOR gate NOR(A) become all low, with the result that theoutput signal INH of the NOR gate NOR(A) becomes high.

The two signals INH and SRE which are inputted into the NAND gate ND(C)are all high, and therefore, the output signal RE of the NAND gate ND(C)becomes low. Therefore, the node N1 comes to have a potential of Vdd.

When the high signal of the node N1 passes through the inverter INV(I),the output signal EQ becomes low. This signal is inverted by theinverter INV(H), and the inverted signal is supplied to the inputterminal of the NOR gate NOR(B) after being delayed for a certain timeperiod by the delay device T. Therefore, the signal SRE becomes lowagain after a certain time period. This low signal is supplied to theinput terminal of the NAND gate ND(C), and therefore, the signal REbecomes high.

Therefore, as described above, the initial values become as follows.That is, the node N1 becomes high, the signal EQ becomes low, the signalSRE becomes low, the signal RE becomes high, and the signal INH becomeshigh.

First, in the case where the address transition signal ATXO is high, thecircuit operates in the following manner.

When the address transition signal ATXO becomes high at a position "A",the transistor Q(B) is turned on, with the result that the node N1 comesto have a potential Vss. This signal is inverted by the inverter INV(I),with the result that the output signal EQ becomes high.

The address transition signal ATXO is inverted by the INV(D) so as tobecome low, and this signal is connected to the input terminal of theNAND gate ND (A). If any one of inputs for a NAND gate is low, then itsoutput becomes high. Therefore, the output of the NAND gate ND (A)becomes high so as to be supplied to the input terminal of the NOR gateNOR(A). If any one of inputs for a NOR gate is high, then its outputbecomes low, and therefore, the output of the NOR gate NOR(A) becomeslow. Thus the signal INH becomes low.

The high signal which is outputted from the inverter INV(I) is invertedby the inverter INV(H) so as to become low, and then, passes through thedelay device T. Therefore, the output of the delay device T ismaintained in a high state until the signal EQ is inverted and passesthrough the delay device T. The output of the delay device T becomes lowafter the elapsing of the delayed time. Therefore, the signal which haspassed through the delay device T becomes high at a time "A", andbecomes low at a time "B" shown in FIG. 2.

The signal which has passed through the delay device T is inputted intothe NOR gate NOR(B) together with the chip selecting inverted low signalCSD. Thus the signal SRE which is an output of the NOR gate NOR(B) ismaintained at a low level as much as the delayed time period of thedelay device T.

If the signal SRE is low, the input of the NAND gate ND(C) becomes high.This means that the PMOS transistor Q(F) and the NMOS transistor Q(G)are all in a turned-off state, and therefore, the potential of the nodeN1 becomes low.

Under this condition, the address transition signal ATXO has become low,while the equalization pulse EQ is an inverted signal of the node N1.Therefore, it maintains a high state up to a time "B" at which thesignal SRE becomes high.

The signal SRE becomes high at the time "B" after being delayed, whilethe signal INH becomes high from the moment when the address transitionsignal ATXO becomes low. Therefore, the two signals which are inputtedinto the NAND gate ND(C) become high, with the result of the signal REbecoming low.

The transistor Q(F) is turned on by the low signal RE, and the signal REis inverted by the inverter INV(G). Consequently, the transistor Q(G) isturned on, and the node N1 becomes high.

If the node N1 becomes low, the signal EQ is outputted as inverted,i.e., with a low level.

Next, in the case where address transition signals are generated with ashort time interval, the circuit operates in the following manner.

The address transition signal ATXO returns to a low level at the time"B" of FIG. 2. Further, the signal EQ is high, and the addresstransition signal ATXO is low. Therefore, when the signal SRE becomeshigh in a state with the signal INH in a high level, the node N1 isshifted to a potential of vdd. If another address transition signal ATX1becomes high at the time "B", the transistor Q(C) is turned on, so thatthe node N1 would be connected to a potential of Vss. That is, the nodeN1 is simultaneously connected to the potential Vdd and the potentialVss, with the result that the power source is short-circuited.

Therefore, the address transition signal ATX1 becomes high, with theresult that the signal INH becomes low, and that the signal RE becomeshigh, thereby turning off the transistors Q(F) and Q(G). Under thiscondition, until the node N1 is prevented from becoming a Vdd potential,and at the time point when the address transition signal ATX1 becomeshigh, the node N1 makes a dc current flow from a Vdd potential to a Vsspotential during the delayed time.

If the next address transition signal ATX1 is shifted to a high state ina fast manner, the node N1 causes a short-circuit between the powersources. Therefore the conventional equalization pulse generatingcircuit loses its effectiveness.

SUMMARY OF THE INVENTION

The present invention is intended to overcome the above describeddisadvantages of the conventional technique.

Therefore it is an object of the present invention to provide a circuitfor generating an equalization pulse for a memory device, in which theconventional problem of having a short circuit between a Vdd potentialand a Vss potential under the case of successive generation of twoaddress transition signals is solved, and in which the equalizationpulses are generated in response to address transition signals so thatthe access time of the memory device is reduced.

In achieving the above and other objects, the equalization pulsegenerating circuit for equalizing the data lines of a memory device byutilizing address transition signals according to the present inventionincludes:

a NAND circuit section for receiving a NAND logic of address transitionsignals under address transitions, to supply a NAND output to anequalization pulse generating node;

a delay circuit section for delaying the output of the equalizationpulse generating node for a certain period of time, to generate delayedsignals; and

a maintaining circuit section for logically summing up the delayedoutputs of the delay circuit section and the NAND output of the NANDcircuit section, to maintain the state of the equalization pulsegenerating node in the same state for a certain period of time.

The circuit for generating equalization pulses for resetting a precedingdata upon changing an address for a memory device according to thepresent invention includes: a NAND circuit section for receiving acompared result of signals, the comparison being made between an addresstransition signal and a responding delayed signal, and an equalizationpulse generating node signal, the NAND circuit section making theequalization pulse generating node high upon encountering any low signalamong the received signals; a delay circuit section with its inputterminal connected to the equalization pulse generating node of the NANDcircuit section, for delaying its input for a time period longer than anaddress transition signal ATD to transmit its output to an equalizationpulse delaying node; a maintaining circuit section with its two inputterminals connected respectively to the equalization pulse generatingnode of the NAND circuit section and to the equalization pulse delayingnode, and with a final compared result of the two signals connected toan input terminal of the NAND circuit section, for maintaining anequalization signal until a certain time period elapses when an addresstransition signal ATD is generated; and a buffer or an inverterconnected to the equalization pulse generating node of the NAND circuitsection, for amplifying the signals.

In the case where there is generated an address transition signal havinga time period shorter than the required time period, the equalizationpulse generating circuit will have a sufficient equalization time.

Further scope of applicability of the present invention will becomeapparent from the detailed description given hereinafter. However, itshould be understood that the detailed description and specificexamples, while indicating preferred embodiments of the invention, aregiven by way of illustration only, since various changes andmodifications within the spirit and scope of the invention will becomeapparent to those skilled in the art from this detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

The above object and other advantages of the present invention willbecome more apparent by describing in detail the preferred embodiment ofthe present invention with reference to the attached drawings in which:

FIG. 1 illustrates a conventional circuit of an equalization pulsegenerator used in a conventional memory device;

FIG. 2 is a timing chart for explaining the conventional circuit of theequalization pulse generator used in the conventional memory device;

FIG. 3 illustrates a circuit of an equalization pulse generatoraccording to an embodiment of the present invention;

FIG. 4 is a timing chart for explaining the circuit of the equalizationpulse generator according to the embodiments of the present invention;FIG. 5 is a timing chart for explaining the equalization pulse generatoraccording to the embodiments of the present invention;

FIG. 6 illustrates another embodiment of the circuit of the equalizationpulse generator according to the present invention; and

FIG. 7 illustrates still another embodiment of the circuit of theequalization pulse generator according to the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIGS. 3, 6 and 7 illustrate the embodiments of the equalization pulsegenerating circuit according to the present invention.

As shown in FIG. 3, the equalization pulse generating circuit forequalizing the data lines of a memory device by utilizing addresstransition signals according to the present invention includes:

a NAND circuit section 12 for receiving a NAND logic of addresstransition signals ATD0, ATD1, ATD2, ATDN under address transitions, soas to supply a NAND output to an equalization pulse generating node N2;

a delay circuit section 13 for delaying the output of the equalizationpulse generating node N2 for a certain period of time, to generatedelayed signals; and

a maintaining circuit section 14 for logically summing up the delayedoutputs of the delay circuit section 13 and the NAND output of the NANDcircuit section 12, so as to maintain the state of the equalizationpulse generating node N2 in the same state for a certain period of time.

The maintaining circuit section 14 includes a first NAND gate ND1 withone of its input terminals receiving a delayed output N3 of the delaycircuit section 13, and with another of its input terminals receivingthe output of the equalization pulse generating node N2, to form NANDlogics for the respective inputs; and a second NAND gate ND2 with itsinput terminals receiving an output of the first NAND gate ND1 and aoutput of the equalization pulse generating node N2, to supply NANDlogics for the respective inputs to one of the input terminals of theNAND circuit section 12.

The delay circuit section 13 includes a plurality of inverters INV1,INV2, . . . , INVN, the number of the inverters being an even number.

The output of the equalization pulse generating node N2 is connected toa buffer or an inverter, so that the buffer or the inverter would outputequalization pulses.

The NAND circuit section 12 includes first transistors Q1, Q2, Q3 . . .Q4 with their gates connected to address transition signals ATD0, ATD1,ATD2 . . . ATDN with their drains connected to an equalization pulsegenerating node N2, and with their sources connected to a power sourceVdd; a second transistor Q5 with its gate connected to an outputterminal of the maintaining circuit section 14, with its drain connectedto the equalization pulse generating node N2 in parallel with thetransistor Q1, and with its source connected to the power source Vdd;third transistors Q6, Q7, Q8 . . . Q9 with their gates connected inseries to the address transition signals ATD0, ATD1, ATD2 . . . ATDN,the transistor Q6 being connected to the equalization pulse generatingnode N2, and a fourth transistor Q10 with its gate connected to theoutput terminal of the maintaining circuit section 14, with its drainconnected to the source of the transistor Q9 in series, and with itssource connected to a potential Vss.

Now the embodiment depicted in FIG. 3, for example, will be described infurther detail.

The circuit of the equalization pulse generator for a memory deviceaccording to the present invention includes a NAND circuit section 12, adelay circuit section 13, a maintaining circuit section 14, and aninverter INV5.

The NAND circuit section 12 includes the first transistors Q1, Q2, Q3, .. . Q4 include

a first transistor Q1 with its gate connected to an address transitionsignal ATD0 of address 0, with its drain connected to an equalizationpulse generating node N2 in parallel, and with its source connected to apower source Vdd;

a second transistor Q2 with its gate connected to an address transitionsignal ATD1 of address 1, with its drain connected to the equalizationpulse generating node N2, and with its source connected to the powersource Vdd;

a third transistor Q3 with its gate connected to an address transitionsignal ATD2 of address 2, with its drain connected to the equalizationpulse generating node N2 in parallel with the transistor Q1, and withits source connected to the power source Vdd; and

a fourth transistor Q4 with its gate connected to an address transitionsignal ATDN of address N, with its drain connected to the equalizationpulse generating node N2 in parallel with the transistor Q1, and withits source connected to the power source Vdd.

The second transistor Q5 has a gate connected to an output terminal ofthe maintaining circuit section 14, a drain connected to theequalization pulse generating node N2 in parallel with the firsttransistor Q1, and a source connected to the power source Vdd.

The NAND circuit section 12 further includes the third transistors Q6 .. . Q9 and the fourth transistor Q10, wherein the third transistors Q6 .. . Q9 include

a first transistor Q6 with its gate connected to the address transitionsignal ATD0 of address 0, and with its source connected to theequalization pulse generating node N2 in series with the firsttransistor Q1;

a second transistor Q7 with its gate connected to the address transitionsignal ATD1 of address 1, and with its drain connected to the source ofthe sixth transistor Q6 in series; a third transistor Q8 with its gateconnected to the address transition signal ATD2 of address 2, and withits drain connected to the source of the transistor Q7 in series; and

a fourth transistor Q9 with its gate connected to the address transitionsignal ATDN of address N, and with its drain connected to the source ofthe eight transistor Q8 in series and

The fourth transistor Q10 has a gate connected to the gate of thetransistor Q5, a drain connected to the source of the transistor Q9 inseries, and with its source connected to a potential Vss.

In the above, the first to fourth of the first transistors Q1-Q4 of theNAND circuit section 12 are P channel enhancement type MOS field effecttransistors, and the number of these transistors being used can bevaried depending on the number of the address transition signals. Thethird to transistors Q6-Q9 are N channel enhancement type MOS fieldeffect transistors, and the number of these transistors being used canbe varied depending on the number of the address transition signals. TheP channel enhancement type MOS field effect transistors are connected inparallel, while the N channel enhancement type field effect transistorsare connected in series.

The delay circuit section 13 includes a first inverter INV1 with itsinput terminal connected to the equalization pulse generating node N2; asecond inverter INV2 with its input terminal connected to an outputterminal of the first inverter INV1; a third inverter INV3 with itsinput terminal connected to an output terminal of the second inverterINV2; and a fourth inverter INV4 with its input terminal connected to anoutput terminal of the third inverter INV3, and with its output terminalconnected to an equalization pulse delaying node N3, the number of theinverters being an even number.

The maintaining circuit section 14 includes a first NAND gate ND1 withits first input terminal connected to the equalization pulse generatingnode N2 of the NAND circuit section 12, and with its second inputterminal connected to the equalization pulse delaying node N3 of thedelay circuit section 13; and

a second NAND gate ND2 with its first input terminal connected to theequalization pulse generating node N2 of the NAND circuit section 12,with its second input terminal connected to an output terminal of thefirst NAND gate, and with its output terminal connected to the gates ofthe tenth transistor Q5 and the tenth transistor Q10 of the NAND circuitsection 12.

The input terminal of the fifth inverter INV5 is connected to theequalization pulse generating node N2 of the NAND circuit section 12,and the fifth inverter INV5 amplifies the equalization pulses to outputa signal EQ.

The circuit of the equalization pulse generator of the present inventionconstituted as above will now be described as to its operationsreferring to the timing chart of FIG. 4.

First, several signals will be defined. The signal ATD0 indicates anaddress transition signal, and when it is low, an address transitionoccurs. The pulse width of the signal ATD0 is shorter than theequalization time period, and when the signal EQ is low, an equalizationoccurs. If the signal EQ comes to have a logic-high, decoding signalsare generated.

When an address transition does not occur, the initial values are asfollows. When all the address transition signals are high, theequalization pulse generating node N2 becomes low. The signal from thenode N2 is inverted by the inverter INV5, and the output signal EQbecomes high. Then, after being delayed for a certain period of time,the equalization delaying node N3 outputs a low level signal.

A low level signal from the equalization delaying node N3 is supplied tothe NAND gate ND1 and, therefore, the output FB of the NAND gate ND1becomes high. Two input signals supplied to the NAND gate ND2 are highand low and, therefore, the output BK of the NAND gate ND2 becomes high.

That is, as shown in FIG. 4, the initial values in a state where anaddress transition is not generated are as follows. In this state, theequalization pulse generating node N2 is low, and the signal EQ becomeshigh. The equalization pulse delaying node N3 is low, and the signal FBis high.

In this state, if an address transition occurs, an address transitionsignal is generated. First, when the signal ATD0 is low as at the timeP1, the operation of the circuit is as follows.

If the signal ATD0 becomes low, the transistor Q1 is turned on, and thetransistor Q6 is turned off, with the result that the equalization pulsegenerating node N2 becomes high. This signal passes through the inverterINV5 to generate the output signal EQ low. Further, a high signal of thenode N2 and a high signal of FB are supplied to the two input terminalsof the NAND gate ND2 at the time P1, and therefore, its output signal BKbecomes low.

At the time P2, even if the signal ATD0 returns to high, the potentialsupplied to the node N3 is low up to a certain time which ispredetermined by the time delay circuit 13. Therefore, the output signalFB of the first NAND gate ND1 is maintained high, and the two signalsinputted into the second NAND gate ND2 are high. Consequently, itsoutput signal BK becomes low, resulting in that the transistor Q5 isturned on, and that the transistor Q10 is turned off. As a result, thenode N2 is maintained in a high state.

The high signal of the Node N2 is delayed for a certain period of timeas it passes through the delay circuit section 13, resulting in theequalization pulse delaying node N3 being shifted to high as at the timeP3. Under this condition, the two signals which are supplied to the NANDgate ND1 of the maintaining circuit section 14 are high, and therefore,the output signal FB of the NAND gate ND1 becomes low. This low signalof the NAND gate ND1 is supplied to the NAND gate ND2, and therefore,its output signal BK becomes high.

Accordingly, all the inputs of the NAND circuit section 14 are high, andits output signal BK is also high. Consequently, the P channelenhancement type MOS field effect transistors Q1, Q2, Q3 . . . Q4 and Q5are turned off, and the N channel enhancement type MOS field effecttransistors Q6, Q7, Q8 . . . Q9 and Q10 are turned on, with the resultthat the potential of the node N2 becomes low.

Therefore, the potential which is supplied to the output terminal EQbecomes as follows. That is, a low signal which is supplied to the nodeN2 is inverted by the inverter INV5 so as to be outputted at a highlevel. Meanwhile, the two inputs of the NAND gate ND2 are high and lowrespectively. Therefore, its output signal FB becomes high.

If the address transition signals are generated with a sufficient timeinterval to make the signals ATD0, ATD1 . . . ATDN low, that is, if anyone of the address transition signals becomes low before the node N3 isshifted to low, the node N2 is shifted from low to high. Therefore, thetwo inputs of the NAND gate ND1 becomes high, so that its output signalFB would become low. This low signal of FB is supplied to the inputterminal of the NAND gate ND2, and therefore, its output signal BKbecomes high to turn on the transistor Q10 and to turn off thetransistor Q5. However, one of the transistors Q1, Q2, Q3 . . . Q4 ofthe NAND circuit section 12 has been turned on by one of the addresstransition signals ATD0 . . . ATDN, and one of the transistors Q6, Q7,Q8 . . . Q9 has been turned off. Therefore, the potential of the node N2becomes high, and the potential of the output terminal EQ becomes low byinverting the input of the inverter INV5.

Now the following case will be described referring to the timing chartof FIG. 5. The case is that, when a certain address signal is changed,two or more address transition signals are generated with certainintervals, so that the address transition signals remain in a low stateeven after the elapsing of the delay time of the delay circuit section13. This case will be described below.

In the case where no address transition occurs, the initial values areas shown on the leftmost side of FIG. 5, wherein the equalization pulsegenerating node N2 is low, the signal EQ is high, the equalization pulsedelaying node N3 is low, the signal FB is high, and the signal BK ishigh.

Under this condition, when the signal ATD0 is low as at the time P4, theoperation of the circuit is as follows.

If the signal ATD0 is low, the transistor Q1 is turned on, and thetransistor Q6 is turned off, resulting in the equalization pulsegenerating node N2 becoming high. This signal passes through theinverter INV5 to make the output signal EQ low. At the time P4, the twosignals, i.e., the high signal of the node N2 and the high signal of FB,are supplied to the NAND gate ND2. Therefore, its output signal BKbecomes low.

Under this condition, if the signal ATD0 returns to high and if thesignal ADT1 becomes low, the potential of the node N3 remains low up toa certain time predetermined by the delay circuit section 13. Therefore,the output signal FB of the NAND gate ND1 is maintained at a high level,with the result of the two input signals of the NAND gate ND2 becominghigh. Therefore, its output signal BK becomes low, so that thetransistor Q5 is turned on and the transistor Q10 is turned off, therebymaintaining the node N2 in a high state.

The high signal of the node N2 passes through the delay circuit section13 so as to be delayed for a certain time period, and the equalizationpulse delaying node N3 is made high as at the time P5. Under thiscondition, the two input signals of the NAND gate ND1 of the maintainingcircuit section 14 are high. Therefore, the output signal FB of the NANDgate ND1 becomes low. This low output signal of the NAND gate ND1 issupplied to the NAND gate ND2 and thus, the output signal BK of the NANDgate ND2 becomes high.

Even though in such a case, the address transition signal ATD1 is in alow state and, therefore, the transistor Q2 is turned on and thetransistor Q7 is turned off. Thus, the node N2 is maintained in a highstate, but the node N2 is shifted to a low state when the addresstransition signal ATD1 returns to a high state as at the time P6.

Consequently, a low signal is inputted into one of the input terminalsof the NAND gate ND1, and the output signal FB of the NAND gate ND1becomes high. Further, a low signal of the node N2 is inverted by theinverter INV5, resulting in the output signal EQ becoming high.

As described above, the circuit of the equalization pulse generatoraccording to the embodiments of the present invention includes a NANDcircuit section, a delay circuit section, a maintaining circuit sectionand an inverter, wherein even in the case where two or more addresstransition signals are generated with small time intervals, the circuitoperates to prevent short circuiting between the potential Vdd and thepotential Vss.

FIG. 6 illustrates a circuit using an inverse logic for generatingequalization pulses according to a second embodiment of the presentinvention. The circuit includes a NAND circuit section ND3, a delaycircuit section 13' and a maintaining circuit section.

The maintaining circuit section includes a second NOR gate NOR2 with oneof its input terminals receiving a delayed output of the delay circuitsection 13', with another of its input terminals receiving the potentialof an equalization pulse generating node N2, to form NOR logics for therespective inputs; and a third NOR gate NOR3 with its input terminalsreceiving the output of the first NOR gate NOR2 and the output of theequalization pulse generating node N2, to form NOR logics for therespective inputs.

The delay circuit section 13' includes a plurality of inverters INV6,INV7 . . . INV11 connected in series, the number of the inverters beingan even number.

The equalization pulse generating node N2 is connected to a buffer BUF1,so that equalization pulses can be output.

The NAND output of the NAND circuit section ND3 is connected to a firstinput terminal of a first NOR gate NOR1, and the output of the third NORgate NOR3 which is the output of the maintaining circuit section isconnected to a second input terminal of the first NOR gate NOR1.Further, the output of the first NOR gate NOR1 is connected to theequalization pulse generating node N2. As shown in FIG. 7, the thirdembodiment of the circuit of the present invention includes a NANDcircuit section ND4 for receiving a NAND logic of address transitionsignals ATD0, ATD1, ATD2 . . . ATDN under address transitions, to supplya NAND output to an equalization pulse generating node N2; a delaycircuit section (INV13, INV14 . . . INV18) for delaying the output ofthe equalization pulse generating node N2 for a certain period of time,to generate delayed signals; and a maintaining circuit section forlogically summing up the delayed outputs N3 of the delay circuit sectionand the NAND output of the NAND circuit section ND4, so as to maintainthe state of the equalization pulse generating node N2 in the same statefor a certain period of time.

The maintaining circuit section includes a first NAND gate ND5 with oneor more of its input terminals connected to the delayed outputs of thedelay circuit section and with its another input terminal connected tothe equalization pulse generating node N2, so as to form NAND logics forthe respective inputs; and a second NAND gate ND6 with its inputterminal connected to the output of the equalization pulse generatingnode N2 and to an output terminal of the first NAND gate ND5, forsupplying the NAND logics for the respective inputs to the inputterminal of the NAND circuit section ND4.

The delay circuit section includes an even number of inverters INV13,INV14 . . . INV18. The output of an even inverter (e.g. INV14) isconnected to the input terminal of the first NAND gate ND5, so that agradual time delay can be achieved. Until all the outputs of the delaycircuit section (which are connected to the input terminals of themaintaining circuit section) are shifted, the output signals aremaintained in a particular logic state.

Further, there is provided a buffer or an inverter INV12 with its inputterminal connected to the equalization pulse generating node N2, andwith its output terminal outputting an equalization pulse EQ afteramplification.

The second and third embodiments of the present invention as depicted inFIGS. 6 and 7, for example, and as described above, operate according tothe wave patterns of FIGS. 4 and 5.

Particularly, in FIG. 7, the delayed outputs of the delay circuitsection are shifted at every moment, and therefore, a gradual time delayis possible. Further, the output signals are maintained at a constantlevel until all the delayed outputs are shifted.

As described above, the circuit of the equalization pulse generatoraccording to the embodiments of the present invention includes a NANDcircuit section, a delay circuit section, a maintaining circuit sectionand an inverter or a buffer. Even in the case where two or more addresstransition signals are generated with short time intervals therebetween,the circuit operates in such a manner that a short circuiting isprevented between the potential Vdd and the potential Vss.

As to the effects of the present invention, when an I/O line is to besufficiently equalized upon encountering an address change, a shortcircuiting due to the generation of two or more address transitionsignals and due to the short time gap therebetween is prevented. Thatis, a flow of a dc current from the potential Vdd to the potential Vss,i.e., a short circuit therebetween, is prevented.

Furthermore, in the case where there is generated an address transitionsignal shorter than the time required for equalization, a sufficientequalization time is provided. That is, even if the address transitionsignal ATD re-appears, an equalization time as much as the delayed timeis provided.

The invention being thus described, it will be obvious that the same maybe varied in many ways. Such variations are not to be regarded as adeparture from the spirit and scope of the invention, and all suchmodifications as would be obvious to one skilled in the art are intendedto be included within the scope of the following claims.

What is claimed is:
 1. A circuit for generating equalization pulses fora memory device, comprising:a NAND circuit section for controlling acharging and discharging of an electric potential at an equalizationpulse generating node according to address transition signals and anoutput of a maintaining circuit section, said NAND circuit sectionincluding a NAND circuit, a first transistor, and a second transistor,said NAND circuit logically NANDing the address transition signals, saidfirst and second transistors controlling an output of the equalizationpulse generating node according to the output of the maintaining circuitsection; a delay circuit section for delaying an output of theequalization pulse generating node for a predetermined time period so asto generate at least one delayed output signal; and the maintainingcircuit section for receiving and logically processing the delayedoutput signal of said delay circuit section with the output of theequalization pulse generating node, so as to maintain the output of theequalization pulse generating node in a same state for a certain periodof time.
 2. The circuit as claimed in claim 1, wherein said maintainingcircuit section includes:a first NAND gate having a first input terminalreceiving the delayed output signal of said delay circuit section, and asecond input terminal receiving the output of the equalization pulsegenerating node, and a second NAND gate having input terminals forreceiving an output of said first NAND gate and the potential of theequalization pulse generating node.
 3. The circuit as claimed in claim2, wherein said delay circuit section includes a plurality of inverters,output terminals of the inverters being connected to said first NANDgate.
 4. The circuit as claimed in claim 1, further comprising:one of abuffer and an inverter, being connected to the equalization pulsegenerating node for outputting the equalization pulses.
 5. The circuitas claimed in claim 1, wherein said NAND circuit section includes:aplurality of third transistors with their gates connected to receive theaddress transition signals, with their drains connected to theequalization pulse generating node, and with their sources connected toa power source, a plurality of fourth transistors with their gatesconnected in series to the address transition signals, with theirsources connected to the equalization pulse generating node, and one ofthe fourth transistors being connected to the equalization pulsegenerating node, the first transistor with its gate connected to theoutput of said maintaining circuit section, with its drain connected toanother one of said fourth transistors in series, and with its sourceconnected to a predetermined potential, and the second transistor withits gate connected to an output of the maintaining circuit section, withits drain connected to said equalization pulse generating node, and withits source connected to the power source.
 6. The circuit as claimed inclaim 5, wherein said third transistors and said second transistor ofsaid NAND circuit section are PMOS field effect transistors.
 7. Thecircuit as claimed in claim 3, wherein the number of said plurality ofinverters is an even number, and output terminals of even numberinverters are connected to said first NAND gate.
 8. The circuit asclaimed in claim 5, wherein said fourth transistors and said firsttransistor are NMOS field effect transistors.
 9. The circuit as claimedin claim 1, wherein said delay circuit section includes a plurality ofinverters connected in series to the equalization pulse generating nodeso as to generate the delayed output signal.
 10. A method of generatingequalization pulses for a memory device, comprising the stepsof:outputting a NAND logic output of address transition signalsgenerated under address transitions to an equalization pulse generatingnode; delaying an output of the equalization pulse generating node for apredetermined time period so as to generate at least one delayed outputsignal; receiving and logically processing the delayed output signalwith the output of the equalization pulse generating node so as togenerate a processed signal and to maintain the output of theequalization pulse generating node in a same state for a certain periodof time; and controlling the state of the equalization pulse generatingnode according to the processed signal from said receiving and logicallyprocessing step, wherein said outputting step includes the stepsof,providing a plurality of first transistors with their gates connectedto receive the address transition signals, with their drains connectedto the equalization pulse generating node, and with their sourcesconnected to a power supply, providing a second transistor with its gateconnected to an output terminal of a maintaining circuit section used insaid outputting step with its drain connected to the equalization pulsegenerating node, and with its source connected to the power source,providing a plurality of third transistors with their gates connected inseries to the address transition signals, one of the third transistorsbeing connected to the equalization pulse generating node, and providinga fourth transistor with its gate connected to the output terminal ofthe maintaining circuit section, with its drain connected to another oneof the third transistors in series, and with its source connected to apredetermined potential.
 11. The method as claimed in claim 10, whereinsaid receiving and logically processing step includes the stepsof:providing a first NAND gate with a first input terminal receiving thedelayed output signal and a second input terminal receiving the outputof the equalization pulse generating node, and providing a second NANDgate with input terminals for receiving an output of the first NAND gateand the output of the equalization pulse generating node.
 12. The methodas claimed in claim 10, wherein said delaying step includes the stepof:providing a plurality of inverters connected in series to theequalization pulse generating node so as to generate the delayed outputsignal.
 13. The method as claimed in claim 10, wherein said outputtingstep includes the steps of:providing a second NOR gate having a firstinput terminal receiving the delayed output signal, and a second inputterminal receiving the output of the equalization pulse generating node,and providing a third NOR gate having input terminals for receiving anoutput the second NOR gate and the output of the equalization pulsegenerating node.
 14. The circuit as claimed in claim 1, wherein duringthe certain period of time, two or more of the address transitionsignals are generated with short time intervals therebetween.
 15. Themethod as claimed in claim 10, wherein said outputting step includes thestep of:providing a third NAND gate for receiving the address transitionsignals and an output of the second NAND gate, and outputting an outputof the third NAND gate to the equalization pulse generating node as theNAND logic output of address transition signals.
 16. The method asclaimed in claim 10, wherein during the certain period of time, two ormore of the address transition signals are generated with short timeintervals therebetween.
 17. The method as claimed in claim 10, whereinsaid controlling step includes the steps of switching the output of theequalization pulse generating node to a high level according to theprocessed signal, and simultaneously preventing diminishing of theoutput of the equalization pulse generating node to a low levelaccording to the processed signal.